1. Field of the Invention
The present invention relates to a semiconductor memory device for decoding an address signal to access a memory cell array.
2. Description of the Related Art
In recent years, as the operating rate of a micro processor increased, speedy operation of a semiconductor memory device has been increasingly demanded. In order to promote speedy operation, it is important to raise accessing speed during ordinary random access. However, promotion of the accessing speed is physically limited. Thus, for example, a semiconductor with a high speed access operation mode called a burst mode has been developed so as to access successive addresses at high speed.
FIG. 1 shows an exemplary configuration of a conventional semiconductor memory device 200 including the burst mode. Herein, a memory cell array 201 of the semiconductor memory device 200 is accessed by an address signal represented by 19 bits (address signal bits A.sub.18 to A.sub.0. The address signal bits A.sub.18 to A.sub.0 are divided into column address signal bits A.sub.6 to A.sub.0 of least significant 7 bits, and row address signal bits A.sub.18 to A.sub.7 of most significant 12 bits.
The column address signal bits A.sub.6 to A.sub.0 and the row address signal bits A.sub.18 to A.sub.7 are externally input and both supplied to a single latch counter 204 via a column address input buffer 202 and a row address input buffer 203, respectively. When an address load enable signal (hereinafter, referred to as an ALE signal) goes from H level (high voltage level) to L level (low voltage level), the address signal bits A.sub.18 to A.sub.0 are loaded to the latch counter 204. The latch counter 204, which loads 19 bits, loads the column address signal bits A.sub.6 to A.sub.0 as its least significant 7 bits and the row address signal bits A.sub.18 to A.sub.7 as its most significant 12 bits in accordance with the ALE signal. Then, the latch counter 204 counts in accordance with a clock signal, using the address signal bits A.sub.18 to A.sub.0 as the initial values. Then, the least significant 7 bits out of the counted results are output as internal column address signal bits A.sub.6 to A.sub.0, and the most significant 12 bits are output as internal row address signal bits A.sub.18 to A.sub.7. In addition to the internal column address signal bits A.sub.6 to A.sub.0 and the internal row address signal bits A.sub.18 to A.sub.7, the latch counter 204 also outputs inverted signal bits A.sub.6 bar to A.sub.0 bar and inverted signal bits A.sub.18 bar to A.sub.7 bar obtained by inverting the address signal bits A.sub.18 to A.sub.0.
The internal column address signal bits A.sub.6 to A.sub.0 and the inverted signal bits A.sub.6 bar to A.sub.0 bar are input to a column predecoder 205. The column predecoder 205 consists of a least significant decoder 205a and a most significant decoder 205b. The 7 internal column address signal bits A.sub.6 to A.sub.0 are further divided into internal column address signal bits A.sub.2 to A.sub.0 of least significant 3 bits and internal column address signal bits A.sub.6 to A.sub.3 of most significant 4 bits. The internal column address signal bits A.sub.2 to A.sub.0 are decoded in the least significant decoder 205a shown in FIG. 2, and the internal column address signal bits A.sub.6 to A.sub.3 are decoded in the most significant decoder 205b shown in FIG. 3. In other words, the internal column address signal bits A.sub.2 to A.sub.0 and the inverted signal bits A.sub.2 bar to A.sub.0 bar of the least significant 3 bits are decoded by the least significant decoder 205a shown in FIG. 2. Then, decoded results CA.sub.7 to CA.sub.0 of 8 bits (=2.sup.3) where any one of the bits is at H level are output. Furthermore, the internal row address signal bits A.sub.6 to A.sub.3 and the inverted signal bits A.sub.6 bar to A.sub.3 bar of the most significant 4 bits are decoded in the most significant decoder 205b shown in FIG. 3. Then, the decoded results of the 16 bits (=2.sup.4) CB.sub.15 to CB.sub.6 where any one of the bits is at H level are output. These decoded results CA.sub.7 to CA.sub.0 and CB.sub.15 to CB.sub.0 are input to a column decoder/selector 206.
The internal row address signal bits A.sub.18 to A.sub.7 and the inverted signal bits A.sub.18 bar to A.sub.7 bar are input to a row predecoder 207. The row predecoder 207 consists of a least significant decoder, an intermediate decoder and a most significant decoder. The internal row address signal bits A.sub.18 and A.sub.7 of 12 bits are further divided into the internal row address signal bits A.sub.10 to A.sub.7 of the least significant 4 bits, the internal row address signal bits A.sub.14 to A.sub.11 of intermediate 4 bits and the internal row address signal bits A.sub.18 to A.sub.15 of the most significant 4 bits. The internal row address signal bits A.sub.10 to A.sub.7, A.sub.14 to A.sub.11, and A.sub.18 and A.sub.15 are decoded in the least significant decoder, the intermediate decoder and the most significant decoder having the same configuration as the decoder shown in FIG. 3. Accordingly, the decoded results of the 16 bits each RA.sub.15 to RA.sub.0, RB.sub.15 to RB.sub.0 and RC.sub.15 to RC.sub.0 are output from the row predecoder 207. These decoded results are further decoded in a row decoder 208, and thus either one of the word lines WLi in the memory cell array 201 is selected.
The column decoder/selector 206 decodes the decoded results output from the column predecoder 205 to select either one of the bit lines in the memory cell array 201. Thus, a memory cell specified by the word line WLi and the selected bit line can be accessed. In the case of a reading operation, data of the selected memory cell is amplified in a sense amplifier 209 and outputs the amplified data to an external data bus or the like via an output buffer 210.
After completing the access by using the externally input address signal bits A.sub.18 to A.sub.0, as shown in FIG. 4, the latch counter 204 performs a counting operation at a time t11 and a time t12 when a clock signal goes high. Then, the latch counter 204 sequentially counts using the address signal bits A.sub.18 to A.sub.0 previously used for accessing the initial values. Generally, since the internal address signal bits A.sub.18 to A.sub.0 of the least significant bits are changed first, the column predecoder 205 decodes the changed internal address signals and sequentially changes the bits of the decoded results CA.sub.7 to CA.sub.0 to be at H level. Each time circulation of the decoded results CA.sub.7 to CA.sub.0 is completed, the bits of the decoded results CB.sub.15 to CB.sub.0 are sequentially changed to be at H level. Accordingly, the column decoder/selector 206 decodes the decoded results CA.sub.7 to CA.sub.0, CB.sub.15 to CB.sub.0 to sequentially select and access another memory cell in the memory cell array 201. When the clock signals are continuously input, the row address signal bits A.sub.18 to A.sub.7 of most significant bits in the latch counter 204 are changed. Thus, the row predecoder 207 and the row decoder 208 perform the decoding operation so that the selection of the word lines WLi are sequentially switched.
As a result, the semiconductor memory device can sequentially access successive addresses of the memory cell array 201 by supplying internally generated clock signals to the latch counter 204.
However, when the address signal bits A.sub.18 to A.sub.0 are counted by the latch counter 204, as described above, the internal column address signal bits A.sub.6 to A.sub.0, and the internal row address signal bits A.sub.18 to A.sub.7 in some cases as well are changed. As a result, not only the column decoder/selector 206 and the row decoder 208, but also the column predecoder 205 and the row predecoder 207 perform the decoding operation. Thus, in a conventional semiconductor memory device, delay time which is generated when the column predecoder 205 and the row predecoder 207 perform the predecoding operation, adversely prevents the promotion of speedy access from being promoted. In addition, since a large amount of charged and discharged current flows during the operation of the column predecoder 205 and the row predecoder 207, power consumption is disadvantageously increased.
In order to solve the above-mentioned problems, a semiconductor memory device 300 using shift registers has been conventionally developed (Japanese Laid-Open Patent Publication No. 6-275073). As shown in FIG. 5, the semiconductor memory device does not include the latch counter 204 as is included in the semiconductor memory device 200. A column decoder/selector 306 includes a column shift register 311, and a row decoder 308 includes a row shift register 312. The column shift register 311 receives decoded results from the columndecoder/selector 306 in parallel in accordance with an ALE signal, and circularly shifts values of the shift data in accordance with a clock signal. The row shift register 312 receives decoded results from the row decoder 308 in parallel in accordance with an ALE signal, and circularly shifts values of the shift data each time circulation of the shift data of the column shift register 311 is completed.
Accordingly, in the semiconductor memory device 300, after the column predecoder 305 and the column decoder/selector 306, or the row predecoder 307 and the row decoder 308 decode the address signal bits A.sub.18 to A.sub.0 once, the successive addresses of the memory cell array 301 can be immediately accessed simply by performing the shifting operation by the column shift register 311 and the row shift register 312 without performing the decoding operation ever again. Thus, it is possible to prevent the delay time in the column predecoder 305 and the row predecoder 307 from obstructing the realization of speedy access or increasing power consumption.
However, in such a semiconductor memory device 300 shown in FIG. 5, the column shift register 311 has 128 (=2.sup.7) shift stages, and the row shift register 312 has 4096 (=2.sup.12) shift stages. Thus, a large shift register with a large number of stages is required to be provided. As a result, a layout area for the shift registers on a chip is disadvantageously too large.
Moreover, as described in Japanese Laid-Open Patent Publication No. 6-275073, in the case where a remedy mechanism for remedying an unsatisfactory cell by using a redundant cell as a substitute for accessing to the address of the unsatisfactory cell is provided, it is necessary to determine whether or not the automatically generated address is directed to the unsatisfactory cell by the counting operation performed by an address counter simultaneously with the shift operation performed by the column shift register 311 and the row shift register 312. Thus, the address counter is required to be provided only for detecting the unsatisfactory cell.